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fnb41560 / FNB41560B2 motion spm? 45 series january 2014 ?2011 fairchild semiconductor corporation 1 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 fnb41560 / FNB41560B2 motion spm ? 45 series features ? ul certified no. e209204 (ul1557) ? 600 v - 15 a 3-phase igbt inverter with integral gate drivers and protection ? low thermal resistance using ceramic substrate ? low-loss, short-circuit rated igbts ? built-in bootstrap diodes and dedicated vs pins sim- plify pcb layout ? built-in ntc thermistor for temperature monitoring ? separate open-emitter pins from low-side igbts for three-phase current sensing ? single-grounded power supply ? isolation rating: 2000 v rms / min. applications ? motion control - home appliance / industrial motor related resources ? an-9070 - motion spm? 45 series users guide ? an-9071 - motion spm? 45 series thermal perfor - mance information ? an-9072 - motion spm? 45 series mounting guid - ance ? rd-344 - reference design (three shunt solution) ? rd-345 - reference design (one shunt solution) general description fnb41560 / FNB41560B2 is an advanced motion spm ? 45 module providing a fully -featured, high-performance inverter output stage for ac induction, bldc, and pmsm motors. these modules integrate optimized gate drive of the built-in igbts to minimize emi and losses, while also providing multiple on-module protection fea- tures including under-voltage lockouts, over-current shutdown, thermal monitoring, and fault reporting. the built-in, high-speed hvic r equires only a single supply voltage and translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's robust short-cir- cuit-rated igbts. separate negative igbt terminals are available for each phase to support the widest variety of control algorithms. package marking and ordering inform ation figure 1. package overview device device marking package packing type quantity fnb41560 fnb41560 spmaa-a26 rail 12 FNB41560B2 FNB41560B2 spmaa-c26 rail 12 free datasheet http://
fnb41560 / FNB41560B2 rev. c3 fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 2 www.fairchildsemi.com integrated power functions ? 600 v - 15 a igbt inverter for three-phase dc / ac power conversion (please refer to figure 3) integrated drive, protection, and system control functions ? for inverter high-side igbts: gate drive circ uit, high-voltage isolated high-speed level shifting control circuit under-voltage lock-out (uvlo) protection ? for inverter low-side igbts: gate driv e circuit, short-circuit protection (scp) control supply circuit under-vol tage lock-out (uvlo) protection ? fault signaling: corresponding to uvlo (low-side supply) and sc faults ? input interface: active-high interface, wor ks with 3.3 / 5 v logic, schmitt trigger input pin configuration figure 2. top view v th (1) r th (2) p(3) u(4) v(5) w(6) n u (7) n v (8) n w (9) v b(u) (26) v s(u) (25) v b(v) (24) v s(v) (23) v b(w) (22) v s(w) (21) in (uh) (20) in (vh) (19) in (wh) (18) v cc(h) (17) com(15) in (ul) (14) in (vl) (13) in (w l) (12) v fo (11) c sc (10) v cc(l) (16) case temperature (t c ) detecting point v th (1) r th (2) p(3) u(4) v(5) w(6) n u (7) n v (8) n w (9) v b(u) (26) v s(u) (25) v b(v) (24) v s(v) (23) v b(w) (22) v s(w) (21) in (uh) (20) in (vh) (19) in (wh) (18) v cc(h) (17) com(15) in (ul) (14) in (vl) (13) in (w l) (12) v fo (11) c sc (10) v cc(l) (16) case temperature (t c ) detecting point free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 3 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 pin descriptions pin number pin name pin description 1v th thermistor bias voltage 2r th series resistor for the use of thermistor (temperature detection) 3 p positive dc-link input 4 u output for u-phase 5 v output for v-phase 6 w output for w-phase 7n u negative dc-link input for u-phase 8n v negative dc-link input for v-phase 9n w negative dc-link input for w-phase 10 c sc capacitor (low-pass filter) for shor t-circuit current detection input 11 v fo fault output 12 in (wl) signal input for low-side w-phase 13 in (vl) signal input for low-side v-phase 14 in (ul) signal input for low-side u-phase 15 com common supply ground 16 v cc(l) low-side common bias voltage for ic and igbts driving 17 v cc(h) high-side common bias voltage for ic and igbts driving 18 in (wh) signal input for high-side w-phase 19 in (vh) signal input for high-side v-phase 20 in (uh) signal input for high-side u-phase 21 v s(w) high-side bias voltage ground for w-phase igbt driving 22 v b(w) high-side bias voltage for w-phase igbt driving 23 v s(v) high-side bias voltage ground fo r v-phase igbt driving 24 v b(v) high-side bias voltage for v-phase igbt driving 25 v s(u) high-side bias voltage ground for u-phase igbt driving 26 v b(u) high-side bias voltage for u-phase igbt driving free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 4 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 internal equivalent circ uit and input/output pins figure 3. internal block diagram 1st notes: 1. inverter high-side is composed of three igbts, freewheeling diodes, and one control ic for each igbt. 2. inverter low-side is composed of three igbts, freewheeling diodes, and one control ic for each igbt. it has gate drive and p rotection functions. 3. inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals. com vcc in(wl) in(vl) in(ul) vfo c(sc) out(wl) out(vl) out(ul) n w (9) n v (8) n u (7) w(6) v (5) u(4) p (3) (25) v s(u) (26) v b(u) (23) v s(v) (24) v b(v) (10) c sc (11) v fo (12) in (wl) (13) in (vl) (14) in (ul) (15) com uvb out(uh) uvs in(uh) wvs wvs out(wh) in(wh) com vcc wvb out(vh) vvs in(vh) v th (1) (19) in (vh) (20) in (uh) (21) v s(w) (22) v b(w) (17) v cc(h) (18) in (wh) r th (2) thermister uvs vvs vvb (16) v cc(l) free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 5 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 absolute maximum ratings (t j = 25c, unless otherwise specified.) inverter part 2nd notes: 1. sinusoidal pwm at v pn = 300 v, v cc = v bs = 15 v, t j 150 , f sw = 20 khz, mi = 0.9, pf = 0.8 2. the maximum junction temperature rating of the power chips integrated within the motion spm ? 45 product is 150 ? c. control part bootstrap diode part total system thermal resistance 2nd notes: 3. for the measurement point of case temperature (t c ), please refer to figure 2. symbol parameter conditions rating unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces collector - emitter voltage 600 v i o,25 output phase current t c = 25c, t j 150c (2nd note 1) 15 a i o,100 output phase current t c = 100c , t j 150c (2nd note 1) 7.5 a i pk output peak phase current t c = 25c, t j 150c, under 1 ms pulse width 22 a p c collector dissipation t c = 25c per chip 34 w t j operating junction temperature (2nd note 2) -40 ~ 150 c symbol parameter conditions rating unit v cc control supply voltage applied between v cc(h) , v cc(l) - com 20 v v bs high - side control bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 20 v v in input signal voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com -0.3 ~ v cc + 0.3 v v fo fault output supply voltage applied between v fo - com -0.3 ~ v cc + 0.3 v i fo fault output current sink current at v fo pin 1 ma v sc current-sensing input voltage applied between c sc - com -0.3 ~ v cc + 0.3 v symbol parameter conditions rating unit v rrm maximum repetitive reverse voltage 600 v i f forward current t c = 25c, t j 150c 0.50 a i fp forward current (peak) t c = 25c, t j 150c, under 1 ms pulse width 1.50 a t j operating junction temperature -40 ~ 150 c symbol parameter conditions rating unit v pn(prot) self-protection supply voltage limit (short-circuit protection capability) v cc = v bs = 13.5 ~ 16.5 v t j = 150c, non-repetitive, < 2 ? s 400 v t stg storage temperature -40 ~ 125 c v iso isolation voltage 60 hz, sinusoidal, ac 1 minute, connect pins to heat sink plate 2000 v rms symbol parameter conditions min. typ. max. unit r th(j-c)q junction to case thermal resistance inverter igbt part (per 1 / 6 module) - - 3.6 c / w r th(j-c)f inverter fwdi part (per 1 / 6 module) - - 4.8 c / w free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 6 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 electrical characteristics (t j = 25c, unless otherwise specified.) inverter part 2nd notes: 4. t on and t off include the propagation delay of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under the given gate driving condition internally. for the detailed information, please see figure 4. figure 4. switching time definition symbol parameter conditions min. typ. max. unit v ce(sat) collector - emitter saturation voltage v cc = v bs = 15 v v in = 5 v i c = 7.5 a, t j = 25c - 1.6 2.1 v v f fwdi forward voltage v in = 0 v i f = 7.5 a, t j = 25c - 1.7 2.2 v hs t on switching times v pn = 300 v, v cc = v bs = 15 v, i c = 7.5 a t j = 25c v in = 0 v ? 5 v, inductive load (2nd note 4) 0.40 0.70 1.20 ? s t c(on) -0.150.40 ? s t off -0.651.15 ? s t c(off) -0.150.40 ? s t rr -0.15- ? s ls t on v pn = 300 v, v cc = v bs = 15 v, i c = 7.5 a t j = 25c v in = 0 v ? 5 v, inductive load (2nd note 4) 0.40 0.70 1.20 ? s t c(on) -0.150.40 ? s t off -0.651.15 ? s t c(off) -0.150.40 ? s t rr -0.10- ? s i ces collector - emitter leakage current v ce = v ces --1ma v ce i c v in t on t c(on) v in(on) 10% i c 10% v ce 90% i c 100% i c t rr 100% i c v ce i c v in t off t c(off) v in(off) 10% v ce 10% i c (a) turn-on (b) turn-off free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 7 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 figure 5. switching loss ch aracteristics (typical) control part 2nd notes: 5. short-circuit protection is functioning only at the low-sides. 6. t th is the temperature of thermister itselt. to know case temperature (t c ), please make the experiment considering your application. symbol parameter conditions min. typ. max. unit i qcch quiescent v cc supply current v cc(h) = 15 v, in (uh,vh,wh) = 0 v v cc(h) - com - - 0.10 ma i qccl v cc(l) = 15 v, in (ul,vl, wl) = 0 v v cc(l) - com - - 2.65 ma i pcch operating v cc supply current v cc(l) = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm sig- nal input for high-side v cc(h) - com - - 0.15 ma i pccl v cc(l) = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm sig- nal input for low-side v cc(l) - com - - 3.65 ma i qbs quiescent v bs supply current v bs = 15 v, in (uh, vh, wh) = 0 v v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) - - 0.30 ma i pbs operating v bs supply current v cc = v bs = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input for high-side v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) - - 2.00 ma v foh fault output voltage v sc = 0 v, v fo circuit: 10 k ? to 5 v pull-up 4.5 - - v v fol v sc = 1 v, v fo circuit: 10 k ? to 5 v pull-up - - 0.5 v v sc(ref) short-circuit current trip level v cc = 15 v (2nd note 5) 0.45 0.50 0.55 v uv ccd supply circuit under-voltage protection detection level 10.5 - 13.0 v uv ccr reset level 11.0 - 13.5 v uv bsd detection level 10.0 - 12.5 v uv bsr reset level 10.5 - 13.0 v t fod fault-out pulse width 30 - - ? s v in(on) on threshold voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com --2.6v v in(off) off threshold voltage 0.8 - - v r th resistance of thermister @t th = 25c, (2nd note 6) - 47 - k ? @t th = 100c - 2.9 - k ? 012345678 0 100 200 300 400 500 inductive load, v pn =300v, v cc =15v, t j =25 igbt turn-on, e on igbt turn-off, e off frd turn-off, e rec switching loss, e sw [uj] collector current, i c [amperes] 012345678 0 100 200 300 400 500 inductive load, v pn =300v, v cc =15v, t j =150 igbt turn-on, e on igbt turn-off, e off frd turn-off, e rec switching loss, e sw [uj] collector current, i c [amperes] free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 8 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 figure. 6. r-t curve of the built-in thermistor bootstrap diode part figure 7. built-in bootstrap diode characteristic 2nd notes: 7. built-in bootstrap diode includes around 15 ? resistance characteristic. symbol parameter conditions min. typ. max. unit v f forward voltage i f = 0.1 a, t c = 25c - 2.5 - v t rr reverse-recovery time i f = 0.1 a, t c = 25c - 80 - ns -20-10 0 102030405060708090100110120 0 50 100 150 200 250 300 350 400 450 500 550 600 r-t curve resistance[k ? ] temperature t th [] 50 60 70 80 90 100 110 120 0 4 8 12 16 20 resistance[k ? ] temperature [ ] r-t curve in 50 ~ 125 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 built-in bootstrap diode v f -i f characteristic t c =25 o c i f [a] v f [v] free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 9 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 recommended oper ating conditions 2nd notes: 8. this product might not make response if input pulse width is less than the recommanded value. figure 8. allowable maximum output current 2nd notes: 9. this allowable output current value is the reference data for the safe operation of this product. this may be different from the actual application and operating condition. symbol parameter conditions min. typ. max. unit v pn supply voltage applied between p - n u , n v , n w - 300 400 v v cc control supply voltage applied between v cc(h) , v cc(l) - com 13.5 15 16.5 v v bs high-side bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13.0 15 18.5 v dv cc / dt, dv bs / dt control supply variation - 1 - 1 v / ? s t dead blanking time for preventing arm-short for each input signal 1.5 - - ? s f pwm pwm input signal - 40 ? c ? t j ? 150c - - 20 khz v sen voltage for current sensing applied between n u , n v , n w - com (including surge-voltage) - 4 4 v p win(on) minimun input pulse width (2nd note 8) 0.5 - - ? s p win(off) 0.5 - - 0 102030405060708090100110120130140 0 1 2 3 4 5 6 7 8 9 10 11 12 13 allowable maximum output current v dc =300v, v cc =v bs =15v t j 150 , t c 125 m.i.=0.9, p.f.=0.8 sinusoidal pwm f sw =15khz f sw =5khz allowable output current, i orms [a rms ] case temperature, t c [ ] free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 10 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 mechanical characteristics and ratings figure 9. flatness measurement position figure 10. mounting screws torque order 2nd notes: 10. do not make over torque when mounting screws. much mounting torque may cause cera mic cracks, as well as bolts and al heat-s ink destruction. 11. avoid one side tightening stress. figure 10 shows the recommended torque order for mounting screws. uneven mounting can cau se the ceramic substrate of the spm ? 45 package to be damaged. the pre-screwing torque is set to 20 ~ 30% of maximum torque rating. parameter conditions min. typ. max. unit device flatness see figure 9 0 - + 120 ? m mounting torque mounting screw: m3 see figure 10 recommended 0.7 n ? m 0.6 0.7 0.8 n ? m recommended 7.1 kg ? cm 6.2 7.1 8.1 kg ? cm weight -11- g 1 2 pre - screwing : 1 2 final screwing : 2 1 1 2 pre - screwing : 1 2 final screwing : 2 1 free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 11 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 time charts of protective function a1 : control supply voltage rises: after the voltage rises uv ccr , the circuits start to operat e when next input is applied. a2 : normal operation: igbt on and carrying current. a3 : under-voltage detection (uv ccd ). a4 : igbt off in spite of control input condition. a5 : fault output operation starts. a6 : under-voltage reset (uv ccr ). a7 : normal operation: igbt on and carrying current. figure 11. under-voltage protection (low-side) b1 : control supply voltage rises: after the voltage reaches uv bsr , the circuits start to operat e when next input is applied. b2 : normal operation: igbt on and carrying current. b3 : under-voltage detection (uv bsd ). b4 : igbt off in spite of control input c ondition, but there is no fault output signal. b5 : under-voltage reset (uv bsr ). b6 : normal operation: igbt on and carrying current. figure 12. under-voltage protection (high-side) input signal output current fault output signal control supply voltage reset uv ccr protection circuit state set reset uv ccd a1 a3 a2 a4 a6 a5 a7 input signal output current fault output signal control supply voltage reset uv bsr protection circuit state set reset uv bsd b1 b3 b2 b4 b6 b5 high-level (no fault output) free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 12 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 (with the external shunt resistance and cr connection) c1 : normal operation: igbt on and carrying current. c2 : short-circuit current detection (sc trigger). c3 : hard igbt gate interrupt. c4 : igbt turns off. c5 : input ?low?: igbt off state. c6 : input ?high?: igbt on state, but during the ac tive period of fault output, the igbt doesn?t turn on. c7 : igbt off state. figure 13. short-circuit protection (low-side operation only) input/output interface circuit figure 14. recommended mcu i/o interface circuit 2nd notes: 12. rc coupling at each input (parts shown dotted) might change depending on the pwm control scheme in the application and the wiring impedance of the application?s printed circuit board. the input signal section of the motion spm ? 45 product integrates a 5 k ?? ( typ.) pull-down resistor. therefore, when using an external filtering resistor, pay atten- tion to the signal voltage drop at input terminal. lower arms control input output current sensing voltage of shunt resistance fault output signal sc reference voltage cr circuit time constant delay sc protection circuit state set reset c6 c7 c3 c2 c1 c8 c4 c5 internal igbt gate - emitter voltage mcu com +5 v (for mcu or control power) ,, in (ul) in (vl) in (wl) ,, in (uh) in (vh) in (wh) v fo r pf = 10 k ? spm free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 13 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 figure 15. typical application circuit 3rd notes: 1) to avoid malfunction, the wiring of each input should be as short as possible (less than 2 - 3 cm). 2) by virtue of integrating an application-specific type of hvic inside the motion spm ? 45 product, direct coupling to mcu terminals without any optocoupler or transformer isola- tion is possible. 3) v fo output is open-drain type. this signal line should be pulled up to the positive side of the mcu or control power supply with a resistor that makes i fo up to 1 ma (please refer to figure 14). 4) c sp15 of around seven times larger than bootstrap capacitor c bs is recommended. 5) input signal is active-high type. there is a 5 k ? resistor inside the ic to pull down each input signal line to gnd. rc coupling circuits is recommanded for the prevention of input signal oscillation. r s c ps time constant should be selected in the range 50 ~ 150 ns ( recommended r s = 100 ? , c ps = 1 nf). 6) to prevent errors of the protection function, the wiring around r f and c sc should be as short as possible. 7) in the short-circuit protection circuit, please select the r f c sc time constant in the range 1.5 ~ 2 ? s. 8) the connection between control gnd line and power gnd line which includes the n u , n v , n w must be connected to only one point. please do not connect the control gnd to the power gnd by the broad pattern. also, the wiring distance between control gnd and power gnd should be as short as possib le. 9) each capacitor should be mounted as close to th e pins of the motion spm 45 product as possible. 10) to prevent surge destruction, the wiring between the smoothing capacitor and the p & gnd pins should be as short as possib le. the use of a high-frequency non-inductive capacitor of around 0.1 ~ 0.22 ? f between the p and gnd pins is recommended. 11) relays are used in almost every systems of electrical equipmen t in home appliances. in these cases, there should be suffic ient distance between the mcu and the relays. 12) the zener diode or transient voltage suppressor should be adopted for the protection of ics from the surge destruction betw een each pair of control supply terminals (recommanded zener diode is 22 v / 1 w, which has the lower zener impedance characteristic than about 15 ? ). 13) please choose the electrolytic capacitor with good temperature characteristic in c bs . also, choose 0.1 ~ 0.2 ? f r-category ceramic capacitors with good temperature and frequency characteristics in c bsc . 14) for the detailed information, please refer to the an-9070, an-9071, an-9072, rd-344, and rd-345. fault +15 v c bs c bsc c bs c bsc c bs c bsc c sp15 c spc15 r pf c bpf r s m v dc c dcs gating uh gating vh gating wh gating ul gating vl gating wl c pf m c u r sw r sv r su u-phase current v-phase current w-phase current r f com vcc in(wl) in(vl) in(ul) vfo csc out(wl) out(vl) out(ul) n w (9) n v (8) n u (7) w (6) v (5) u (4) p (3) (25) v s(u) (26) v b(u) (23) v s(v) (24) v b(v) (10) c sc (11) v fo (14) in (ul) (13) in (vl) (12) in (wl) (20) in (uh) (19) in (vh) (21) v s(w) (22) v b(w) (17) v cc(h) (18) in (wh) input signal for short-circuit protection c sc r s r s r s r s r s r s c ps c ps c ps c ps c ps c ps in(wh) in(vh) in(uh) com vcc vs(w) vs(v) vs(u) vs(v) vs(u) vs(w) vb(u) vb(v) vb(w) (15) com out(wh) out(vh) out(uh) lvic hvic (1) v th (2) r th r th thermistor temp. monitoring (16) v cc(l) +5 v c spc05 c sp05 free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 14 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 detailed package outlin e drawings (fnb41560) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or data on the drawing and contact a fairchildsemiconductor representative to veri fy or obtain the most recent revision. package s pecifications do not expand the terms of fa irchild?s worldwide therm and conditions, specifically the the warranty therein, which covers fairchild products. always visit fairchild semiconduct or?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/mo/mod26aa.pdf free datasheet http://
fnb41560 / FNB41560B2 motion spm? 45 series ?2011 fairchild semiconductor corporation 15 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 detailed package outline drawings (FNB41560B2 long terminal type) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or data on the drawing and contact a fairchildsemiconductor representative to veri fy or obtain the most recent revision. package s pecifications do not expand the terms of fa irchild?s worldwide therm and conditions, specifically the the warranty therein, which covers fairchild products. always visit fairchild semiconduct or?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/mo/mod26ac.pdf free datasheet http://
?2011 fairchild semiconductor corporation 16 www.fairchildsemi.com fnb41560 / FNB41560B2 rev. c3 free datasheet http://

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